Multimodal biometric authentication systems: exploring EEG and signature
Das B.B., Reddy C.V., Matha U., Yandapalli C., Ram S.K.
Article, Cognitive Neurodynamics, 2026, DOI Link
View abstract ⏷
Biometric traits are unique characteristics of an individual’s body or behavior that can be used for identification and authentication. Biometric authentication uses unique physiological and behavioral traits for secure identity verification. Traditional unimodal biometric authentication systems often suffer from spoofing attacks, sensor noise, forgery, and environmental dependencies. To overcome these limitations, our work presents multimodal biometric authentication integrated with the characteristics of electroencephalograph (EEG) signals and handwritten signatures to enhance security, efficiency, and robustness. EEG-based authentication uses the brainwave patterns’ intrinsic and unforgeable nature, while signature recognition demonstrates an additional behavioral trait for effectiveness. Our system processes EEG data of an individual with 14-channel readings, and the signature with the images ensures a seamless fusion of both modalities.Combining physiological and behavioral biometrics, our approach will significantly decrease the risk of unimodal authentication, including forgery, spoofing, and sensor failures. Our system, evaluated on a dataset of 30 subjects with genuine and forged data, demonstrates a 97% accuracy. Designed for small organizations, the modular structure, low computation algorithms, and simplicity of the hardware promote deployment scalability.
Everything You Wanted to Know about Secure Energy Harvesting Techniques for IoT Devices: A Review
Amala C., Subbarao B., Sivaji M., Ojha T., Bandana Das B., Mohanty S.P., Ram S.K.
Review, IEEE Sensors Journal, 2025, DOI Link
View abstract ⏷
In recent years, the rapid growth in urbanization and smart cities has been empowered by efficient and intelligent solutions in areas such as transportation, governance, and smart banking. These applications feature large-scale Internet of Things (IoT) deployment of wirelessly connected smart embedded devices with sensors and actuators. Providing adequate energy to power this large number of IoT devices remains a crucial challenge. In this regard, energy harvesting (EH) emerges as a promising approach that converts ambient energy into usable electrical energy, allowing IoT devices to function autonomously and sustainably, thereby reducing maintenance efforts while enhancing the overall system reliability. Although EH systems offer significant advantages, they are also vulnerable to various threats and attacks that underscore the need to design secure and reliable EH solutions. In this article, we comprehensively review the state-of-the-art EH techniques and associated security aspects. We discuss current research on EM techniques, optimization algorithms, and the challenges involved in energy-efficient routing within IoT. Next, we analyze the existing EH methods in two directions - energy extraction and energy storage. In terms of energy extraction from renewable sources, we review the maximum power point tracking (MPPT) algorithms used in IoT devices. Then, we explore the energy storage capabilities of sensor nodes, which are crucial for consistent operation. Furthermore, we discuss the security and reliability mechanisms within IoT EH frameworks, identifying the threats and countermeasures.We conclude the survey by discussing the future research directions and listing a few open problems.
SThing: A Novel Configurable Ring Oscillator Based PUF for Hardware-Assisted Security and Recycled IC Detection
Ram S.K., Sahoo S.R., Das B.B., Mahapatra K., Mohanty S.P.
Article, IEEE Access, 2025, DOI Link
View abstract ⏷
The ring oscillator (RO) is widely used to address different hardware security issues. For example, the RO-based physical unclonable function (PUF) generates a secure and reliable key for the cryptographic application, and the RO-based aging sensor is used for the efficient detection of recycled ICs. In this paper, a CMOS inverter with two voltage control signals is used to design a configurable RO (CRO). With its control signals, the proposed CRO can both accelerate and lower the impact of aging on the oscillation frequency. This vital feature of the proposed CRO makes it suitable for use in PUFs and RO-based sensors. The performance of both the proposed modified architecture, i.e., CRO PUF and CRO sensor, is evaluated in 90 nm CMOS technology. The aging tolerant feature of the proposed CRO enhances the reliability of CRO PUF. Similarly, the aging acceleration property of CRO improves the rate of detection of recycled ICs. Finally, both the proposed architectures are area and power-efficient compared to standard architectures.
Eternal-Thing 3.0: Mixed-Mode SoC for Energy Harvesting System Towards Sustainable IoT
Ram S.K., Yadav S.M., Kumar J., Singh P., Das B.B.
Article, IEEE Access, 2025, DOI Link
View abstract ⏷
The power requirement in IoT is essential to fulfill the energy demand of the power-hungry sensors at end nodes. The use of fixed batteries restricts sustainability and makes the system costly. This work presents a battery-less solar energy harvesting system (EHS). Designing a state-of-the-art EHS needs a lot of exercise. Proper modeling of each unit makes the system robust and can be tuned at every stage to get an optimum result. The proposed EHS comprises a clock generator, DC-DC converters, analog-to-digital converters (ADCs), a maximum power point tracking (MPPT) unit, and a digital controller. The DC-DC converter and ADCs are designed in Verilog-A. The MPPT module digital controller is designed using Verilog HDL. The digital controller decides the mode of operation of the EHS based on power availability. Verilog-AMS allows us to do the mixed-mode simulation very early, so errors can only be eliminated in the initial stages at the circuit level. The proposed EHS is simulated in the Cadence Virtuoso AMS Designer Simulator (using the Incisive Run tool). The input solar voltage is 1 V to 1.5 V, and the output is 3 V to 3.5 V. The EHS provides supply voltages of 3.3 V, 1.8 V, and 1 V to the end node devices in IoT. The EHS is further designed with the parameters obtained from modeling in Cadence using virtuoso (for analog circuits) and genus (for digital circuits) and finally combined in Innovous (mixed-mode tool) for tape-out.
A Framework for Robust Person Identification using Brain Signals
Samineni A.S.S., Venu P., Lolugu C.S.V.N., Kotharu B., Pachipulusu M.C., Ram S.K., Das B.B., Mohanty S.P.
Conference paper, Proceedings - 2024 OITS International Conference on Information Technology, OCIT 2024, 2024, DOI Link
View abstract ⏷
Biometric authentication is pivotal in identifying individuals with unique physiological or behavioral characteristics. General recognition methods, such as fingerprint, voice, iris, and face recognition, are widely used but have significant flaws. These can be sensitive to spoofing, raise privacy concerns, and often struggle in certain environments. To fix these shortcomings, we proposed a novel biometric method: Electroencephalogram (EEG) authentication. Electroencephalogram (EEG) technology measures brainwave activity through electrodes and is known for its reliability, resistance to forgery, and inherent uniqueness, similar to fingerprints. EEG is particularly significant for liveness detection, making it a strong candidate for robust biometric authentication in high-security applications. This study utilizes a publicly available dataset consisting of EEG data from 109 subjects. The raw data is first scaled and then analyzed using various classifiers, such as κ-nearest neighbors (κ-NN), Auto-Encoder with κ-NN, and Convolutional Neural Networks (CNN). The model’s performance is evaluated under four different conditions based on the subjects’ activities, with the CNN achieving an authentication accuracy of 92%.
An Off-chip Based PUF for Robust Security in FPGA Based IoT Systems
Amala C., Subbarao B., Ojha T., Das B.B., Ram S.K., Mohanty S.P.
Conference paper, Proceedings - 2024 OITS International Conference on Information Technology, OCIT 2024, 2024, DOI Link
View abstract ⏷
In this paper, a new promising hardware security primitive physically unclonable Function (PUF) is implemented to generate a unique secret key for each SOC Board. Especially FPGA-based, IoT is most widely used for different applications. Several types of PUFs are designed and implemented due to their remarkable performance for hardware security applications. In most of the PUFs ring oscillators are mostly preferred, but these are for limited input. In this context, we proposed a new PUF without increasing the size of the hardware implementation, and power. In this research, we used simple XNOR and XOR gates to increase the number of inputs. Even though it is a weak PUF, generally, weak PUFs is the most preferable for implementation, and by increasing CRPs, one can make a weak PUF as strong. This Arbitrary PUF is implemented on the Artix-7 AC701 Evaluation platform using Xilinx Vivado 2019.1.
Fortified-SoC: A Novel Approach Towards Trojan Resilient System-on-Chip Design
Subbarao B., Amala C., Das B.B., Ram S.K., Mohanty S.P.
Conference paper, Proceedings - 10th IEEE International Symposium on Smart Electronic Systems, iSES 2024, 2024, DOI Link
View abstract ⏷
This research paper investigates a hardware-type attack on System-on-Chips (SoCs) involving a trigger and a payload. A stealthy and controllable fabrication time attack, A2, is demonstrated, and a circuit is developed based on charge accumulation from rare events within the system. When voltage gets buildup due to charge coupling, the payload has been activated, leading to a privilege-escalation attack. In this research, a specific analog hardware Trojan (A2) detection and mitigation circuit is designed. This Trojan affects the circuit performance by targeting sensitive wires (like reset) in SoCs. This paper presents a method for detecting the Trojan and implementing proper mitigation techniques to safeguard SoCs from malicious attacks.
Security-by-Design For Smart Electronics
Yanambaka V.P., Swain A.K., Ram S.K., Mohanty S.
Conference paper, Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, 2024, DOI Link
Eternal-thing 2.0: Analog-Trojan-resilient Ripple-less Solar Harvesting System for Sustainable IoT
Ram S.K., Sahoo S.R., Das B.B., Mahapatra K., Mohanty S.P.
Article, ACM Journal on Emerging Technologies in Computing Systems, 2023, DOI Link
View abstract ⏷
Recently, harvesting natural energy is gaining more attention than other conventional approaches for sustainable IoT. System on chip power requirement for the internet of things (IoT) and generating higher voltages on chip is a massive challenge for on-chip peripherals and systems. In this article, an on-chip reliable energy-harvesting system (EHS) is designed for IoT with an inductor-free methodology. The control section monitors the computational load and the recharging of the battery/super-capacitor. An efficient maximum power point tracking algorithm is also used to avoid quiescent power consumption. The reliability of the proposed EHS is improved by using an aging tolerant ring oscillator. The effect of Trojan on the performance of energy-harvesting system is analyzed, and proper detection and mitigation mechanism is proposed. Finally, the proposed ripple mitigation techniques further improves the performance of the aging sensor. The proposed EHS is designed and simulated in CMOS 90-nm technology. The output voltage is in the range of 3-3.55 V with an input 1-1.5 V with a power throughput of 0-22 μW. The EHS consumes power under the ultra-low-power requirements of IoT smart nodes.
A Novel Circuit-Level Method for Hardware Trojan Detection in Digital Designs
Moulee S.C., Ramesh S.R., Ram S.K.
Conference paper, 2023 10th IEEE Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering, UPCON 2023, 2023, DOI Link
View abstract ⏷
The increased dependency on the technology also increases the possible exploitation of a device by malicious agents. The protection against the insertion of Hardware Trojans in the integrated circuits (ICs) is becoming the biggest concern in the current manufacturing processes. The functionality of a Hardware Trojan is to either modify the circuit's standard running functionality or leak any confidential information from the circuit. Hardware Trojans can be detected in both pre-silicon and post-silicon stages, but vulnerability is more in the postsilicon stage. This research aims to detect a hardware Trojan with a zero probability of getting triggered, no increase in area overhead and without activating it with the help of a golden response. A new method for hardware Trojan detection is proposed here using the power feature, RC parasitic extraction, and machine learning (ML)- based clustering techniques. It can not only detect the presence of a Hardware Trojan but also detect the nets in which it is connected. Experiments are carried out on seven ISCAS'85 and seven ISCAS'89 circuits; out of 14 circuits, results were found satisfactory in 13 circuits.
Energy-efficient adaptive sensing for Cognitive Radio Sensor Network in the presence of Primary User Emulation Attack
J. B.V., Ram S.K., Deepan
Article, Computers and Electrical Engineering, 2023, DOI Link
View abstract ⏷
A Cognitive Radio Sensor Network (CRSN) is a promising technology incorporating cognitive radio in traditional wireless sensor networks. In general, Primary User Emulation Attack (PUEA) is becoming the major bottleneck for implementing CRSN in reality. In CRSN-PUEA, malicious users are also equipped with a Spectrum Sensing capability, the so-called smart PEUA, which further complicates the spectrum access of Cognitive Users (CU). In this paper, we propose a novel Energy-Efficient Adaptive Sensing (EEAS) technique for CRSN to overcome the spectrum access problem in the presence of PUEA. The proposed EEAS enhances the sensing accuracy by differentiating the PUEA and Primary User signals that, reduce the sensing error probability and enhance the underlying system model's throughput and energy efficiency. The numerical results show that the proposed EEAS technique has improved the throughput and energy efficiency by about 12% and 44%, respectively, compared to the state-of-the-art works in the field of PUEA-CRSN. In addition, it is observed that the sensing error probability is reduced by 22%. Furthermore, a Software Defined Radio (SDR) based hardware system setup has been developed to verify the functionality of the proposed system model.
Performance assessment of three-phase PV tied NPC multilevel inverter based UPQC
Mohan H.M., Dash S.K., Ram S.K., Caesarendra W.
Conference paper, 2022 International Conference on Intelligent Controller and Computing for Smart Power, ICICCSP 2022, 2022, DOI Link
View abstract ⏷
The surge in the integration of renewable energy sources with the grid has prompted a significant increase in research into power conditioners for high-quality energy supply. During both balanced and unbalanced conditions, power conditioners are used to provide not just quality power but also balanced rms voltage and current towards the demand at a constant frequency. A Photovoltaic (PV) connected Unified Power Quality Controller (UPQC) is designed with a neutral point clamped (NPC) multilevel inverter for improving the power quality is presented. In order to design the controllers for the various power converters, various control strategies were used. A three-phase four-wire NPC multilevel inverter is made into a power quality conditioner with Synchronous Reference Frame (SRF) theory. The UPQC is the most relevant device in compensating the power quality issues for sensitive and critical loads. The DC capacitor linked voltage is balanced by using a PI controller. The designed system is simulated by using MATLAB/Simulink software and performance is found satisfactory during various conditions.
SVM and Ensemble-SVM in EEG-Based Person Identification
Das B.B., Ram S.K., Pati B., Panigrahi C.R., Babu K.S., Mohapatra R.K.
Conference paper, Advances in Intelligent Systems and Computing, 2021, DOI Link
View abstract ⏷
Biometric person identification is getting more effective and popular because of Electroencephalography (EEG). EEG signals can be captured from human scalp invasively or non-invasively with the help of electrodes. EEG-based biometric system is more secure and unique for person identification. In this paper, we have used two different states to explore the adaptive and uniqueness of the EEG-based biometric system. We have used Eyes Open (EO) state as well as Eyes Closed (EC) state of a EEG motor imagery publicly available dataset of 109 users.The model is trained and tested with EO and EC states alternatively to prove the reliability and robustness of the model. The biometric person identification model has been designed using Support Vector machine (SVM) for classification. We achieved a notable person identification rate of 96% (EO) and 91.78% (EC) using SVM with Radial Basis Function (RBF) kernel. We have also used Ensemble Support Vector Machine (ESVM) to enhance the performance of person identification and observed the average performance accuracy of 96.16% with n number of classifier.
SEHS: Solar Energy Harvesting System for IoT Edge Node Devices
Ram S.K., Das B.B., Pati B., Panigrahi C.R., Mahapatra K.K.
Conference paper, Advances in Intelligent Systems and Computing, 2021, DOI Link
View abstract ⏷
In IoT (internet of things) realm, sensors need an uninterrupted power supply for continuous operation. This paper presents an on-chip solar EHS (SEHS) design for IoT edge node devices. For matching the impedance between the solar cell and converter, CVM technique is adopted. The energy efficient hill-climbing algorithm (HCA) is adopted to follow the maximum power point (MPP). The control section takes care of the MPPT procedure, and computational load along with the charging of the supercapacitor. LDO (low dropout regulators) is used to generate various voltages needed by the sensors. The proposed system is capable of providing power supply to various edge node devices in IoT. The SEHS is designed in CMOS 180 nm technology. The output voltage is in the range of 1.2–3.55 V with an input of 1–1.5 V. The SEHS is consuming 25 W of power, which is within the ultra-low-power range in IoT.
Eternal-Thing: A Secure Aging-Aware Solar-Energy Harvester Thing for Sustainable IoT
Ram S.K., Sahoo S.R., Das B.B., Mahapatra K., Mohanty S.P.
Article, IEEE Transactions on Sustainable Computing, 2021, DOI Link
View abstract ⏷
Security and energy-consumptiont are two conflicting challenges in the design and operation of the smart cities that use Internet-of-Things (IoT). Providing power to IoT things (i.e., sensors and their communications) is a challenge as battery have a limited lifetime, and their maintenance and disposal are costly and hazardous. System on chip (SoC) power requirements for IoT ultra-low-power realm is different and is a challenge for the design engineers to provide uninterrupted power. In this paper, a paradigm shift research that addresses a secure self-sustainable solar-energy harvesting system (EHS) with a security mechanism is proposed. This design incorporates Physically Unclonable Functions (PUFs) for the security of EHS along with an aging sensor for recycled IC detection. The control unit monitors the computational load, recharging of the battery, and security mechanism. Capacitor value modulation (CVM) is used for impedance matching between solar cell and converter during maximum power point tracking (MPPT) to avoid quiescent power consumption. The existing resources of EHS used for designing the PUFs and aging sensor. The secure EHS is designed and fabricated in CMOS 90nm technology. The resulting output is in the range of 3-3.55 V with an input 1-1.5 V. The proposed EHS is consuming 22 μW of power, that satisfies the ultra-low-power requirements of IoT smart nodes.
Energy Perspectives in IoT Driven Smart Villages and Smart Cities
Ram S.K., Das B.B., Mahapatra K., Mohanty S.P., Choppali U.
Article, IEEE Consumer Electronics Magazine, 2021, DOI Link
View abstract ⏷
The Internet-of-Things (IoT) consists of a large number of different and heterogeneous devicesunder one umbrella. Building a typical architecture for the devices used in IoT is a challenge due to the involvement of a vast number of devices, layers, protocols, middleware, and software. The sensors in IoT have to monitor the activities regularly, making the end node devices energy hungry. Traditional fixed batteries get drained out in limited time, requiring continuous replacement, thereby increasing the budget. This article focuses on consumer technologies in the perspective of IoT computing targeted for smart villages and smart cities. The article discusses security-by-design (SbD) concepts in the energy harvester technologies for sustainable and secured IoT with uninterruptedenergy resource smart villages and smart cities.
A solar based power module for battery-less IoT sensors towards sustainable smart cities
Ram S.K., Chourasia S., Das B.B., Swain A.K., Mahapatra K., Mohanty S.
Conference paper, Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, 2020, DOI Link
View abstract ⏷
This paper presents an ultra-low-power solar energy harvesting system with a power management module (SEHS-PMU) for the Internet-of-Things (IoT) applications. The voltages generated are suitable for the IoT sensors used for smart cities as well as Internet-of-Medical-Things (IoMT) based biomedical applications. The SEHS-PMU is harvesting energy from the solar cell, and it can provide regulated voltages of 3.3 V, 1.8 V, 1 V, and 0.5 V. The harvesting mechanism leads to battery-less IoT, and is safe for the humanity and environment. Charge pumps (CP) are used as a boost and buck converter, which is suitable for monolithic integration. Low drop-out regulators (LDOs) are used for regulating the loads. A digital controller controls the selection of loads as per requirement for saving the power. The SEHS-PMU is designed in CMOS 180 nm technology library.
A spatio-temporal model for EEG-based person identification
Das B.B., Kumar P., Kar D., Ram S.K., Babu K.S., Mohapatra R.K.
Article, Multimedia Tools and Applications, 2019, DOI Link
View abstract ⏷
Biometric representation of humans often requires the tasks such as identification and verification. This can be done using various modalities such as fingerprint, face, retina, voice, etc. However, existing biometric systems are vulnerable to various security attacks. Recently, Electroencephalography (EEG) is considered to be one of the alternatives to develop a robust biometric system. Brain activities represented by EEG signals are more sensitive, secure, and difficult to copy and steal. In this paper, we propose a spatio-temporal dense architecture for EEG-based person identification. Firstly, raw EEG are processed to extract robust and informative spatial features using Convolutional Neural Networks (CNN) as they are known for automatic feature extraction from the raw data. Then, a Long short-term memory (LSTM) network is utilized to process temporal data and person identification is carried out. The experiment has been carried out on a publicly available dataset consisting of EEG of 109 subjects. The architecture is tested on two baseline situations, i.e., eye closed (EC) and the eye opened (EO). Person identification rates of 99.95% and 98% have been recorded for EC and EO states using the proposed scheme. Experimental results demonstrate the robustness of the proposed scheme in terms of person identification and outstrip existing works.
Ultra-low power solar energy harvester for IoT edge node devices
Conference paper, Proceedings - 2019 IEEE International Symposium on Smart Electronic Systems, iSES 2019, 2019, DOI Link
View abstract ⏷
An Ultra-low power solar energy harvesting system (EHS) for IoT end node devices is presented in this paper. To provide an uninterrupted power supply to IoT nodes is a challenge. The solar cell is used as an input source and this low input voltage is boosted by using the DC-DC converter. The charge pump is used as a voltage booster and the impedance matching between the solar cell and the converter is achieved through frequency tuning and capacitor value modulation. A hill-climbing technique is used for maximum power point (MPP) achievement. The EHS designed is self-sustainable and the output is in the range of 3-3.55 V with an input of 1-1.5 V. The EHS is designed in CMOS 90 nm technology library. The simulation results validate the proposed concept and the EHS is consuming a power of 22 μW, which is within the Ultra-low power range of IoT smart nodes.
Energy efficient ultra low power solar harvesting system design with MPPT for IOT edge node devices
Ram S.K., Sahoo S.R., Sudeendra K., Mahapatra K.
Conference paper, Proceedings - 2018 IEEE 4th International Symposium on Smart Electronic Systems, iSES 2018, 2018, DOI Link
View abstract ⏷
Towards designing an on-chip harvesting system design for IoT, an inductor free methodology is proposed. The solar system behavior is analyzed and proper control algorithm for maximum power point tracking (MPPT) is adopted. The control section monitors the computational circuit and recharging of the battery. Capacitor value modulation (CVM) is used for impedance matching. The conversion efficiency of the DC-DC converter is from 87% to 97%. The resulting output is in the range of 3-3.55V.
A new approach to design digital controller for three phase active power line conditioner for harmonic compensation using 8051 microcontroller
Conference paper, Proceedings of the International Conference on Inventive Computation Technologies, ICICT 2016, 2016, DOI Link
View abstract ⏷
The non-linear devices used in the present environment like computers, printers, lasers, smps, rectifiers etc. pollutes the power system by harmonics and reactive power. Due to the presence of harmonics in the power system a number of undesirable effects caused in the distribution network. To find the solution for this the active power filter (APF) is one of the suitable solutions, which compensates Harmonics as well as reactive power simultaneously. This paper presents a active power line conditioning system to improve the power quality in the distribution network and implementation of a digital controller using 8051 microcontroller. The active power line conditioner is implemented with Pulse Width Modulation (PWM) based current controlled voltage source inverter (VSI). The Digital Controller is designed using MCS 8051 microcontroller which becomes independent of process technology. Synchronous reference frame (SRF) is used for generation of reference current. The PI current algorithm is implemented using MATLAB platform. The shunt APF is modeled and investigated under different unbalanced non-linear load conditions in MATLAB/SIMULINK. The simulation results reveals that the active power filter is efficiently compensating the current harmonics and reactive power in the distribution network. The APF system is in compliance with the IEEE 519 and IEC 61000-3 recommended standards.
Digital controller design for three phase active power filter for harmonic and reactive power compensation using FPGA and system generator
Conference paper, Proceedings of the International Conference on Inventive Computation Technologies, ICICT 2016, 2016, DOI Link
View abstract ⏷
The harmonics and the reactive power is a major concern in power distribution system. The extensive use of the non-linear loads in the present context as computers, SMPS, Rectifiers etc. give rise to harmonics and reactive power in the power system. These will cause a large undesirable effects like equipment heating, damaging devices etc. To compensate harmonics and reactive power, active power filter (APF) is widely used. This paper presents a three-phase APF for power line conditioning (PLC) system to improve the power quality in the point of common coupling (PCC). It also consists of a controller to control the APF. The hysteresis current controller (HCC) is used to generate the switching pulses for the voltage source inverter. VHDL is used to design a digital controller as it is independent of process technology. To generate the reference current synchronous reference frame (SRF) theory is used. The PI current algorithm (using FSM+DATAPATH) and the HCC are designed using VHDL codes and implemented on FPGA for hardware. The three phase APF is modeled, tested and investigated under different unbalanced non linear conditions using MATLAB/SIMULINK environment. The simulation results justify that the APF is compensating the harmonics and reactive power at the PCC. The APF system is in compliance with IEEE 519 and IEC 61000-3 recommended harmonic standards.
Localization using beacon in wireless sensor networks to detect faulty nodes and accuracy improvement through DV-Hop algorithm
Conference paper, Proceedings of the International Conference on Inventive Computation Technologies, ICICT 2016, 2016, DOI Link
View abstract ⏷
Now a days, Wireless Sensor Networks (WSN) are emerging as a challenging and interesting area. Wireless Sensor Network consists of a large number of heterogeneous or homogeneous sensor nodes which communicates through wireless medium and works together to sense or monitor the environment. The number of sensor nodes in a network can vary from hundreds to thousands. The node senses data from environment and sends these data to the gateway node. Mostly WSNs are used for applications such as military surveillance and disaster monitoring. WSNs are multi-hop networks, which depend on the intermediate nodes to relay the data packet to the destination. These nodes are equipped with lesser memory, limited battery power, little computation capability, small range of communication and need a secured and efficient routing path to forward the incoming packet delay by data aggregation) and multipath sensor networks to increase the resilience and reliability of the network. The localization information is crucial for the operation of WSN. There are mainly two types of Localization algorithms. The Range-based localization algorithm has requirements on hardware, thus is expensive to be implemented in practice. The Range-free localization algorithm reduces the hardware cost. In this paper we locate known nodes by placement (DV Hop) in various locations for best result. Our algorithm improves the localization accuracy compared with previous algorithms, which has been demonstrated by the simulating results.
Comparison of different control strategy of conventional and digital controller for active power line conditioner (APLC) for harmonic compensation
Conference paper, 12th International Conference on Environment and Electrical Engineering, EEEIC 2013, 2013, DOI Link
View abstract ⏷
Various electronic circuits such as inverters, choppers, cyclo-converters, SMPS used by industrial and domestic purposes are non-linear in nature, which makes the load current to be distorted, causing undesirable effects like heating, equipment damages, EMI related problems in power system. The active power filter (APF) is the best solution for eliminating the harmonics caused by the non-linear loads. This paper presents about a three-phase four-wire active power filter for power line conditioning to improve power quality in the distribution network and implementation of a digitally controlled APF. The active power filter is implemented with PWM based current controlled voltage source inverter (VSI).The switching signals for APF are generated through proposed three-level hysteresis current controller (HCC). The shunt APF system is modeled and investigated under different unbalanced non-linear load conditions using MATLAB program. The Controller Design using Hardware Description Language (VHDL or VERILOG) becomes independent of process technology. Synchronous reference frame (SRF) is used for generation of reference current. Both PI current algorithm and HCC are written in VHDL code and implemented using FPGA platform. © 2013 IEEE.
Three level hysteresis current controller based active power filter for harmonic compensation
Karuppanan P., Ram S.K., Mahapatra K.
Conference paper, 2011 International Conference on Emerging Trends in Electrical and Computer Technology, ICETECT 2011, 2011, DOI Link
View abstract ⏷
This paper present three-phase four-wire active filter for power line conditioning (PLC) to improve power quality in the distribution network. The active power filter (APF) is implemented with PWM based current controlled voltage source inverter (VSI). This VSI switching signals are generated through proposed three-level hysteresis current controller (HCC) that achieves significant reduction in the magnitude and variation of the switching frequency; it is indicating improved performance compared to 2-level HCC. The shunt APLC system is modeled and investigated under different unbalanced non-linear load conditions using Matlab programs. The simulation results reveal that the active power filter is effectively compensating the current harmonics and reactive power at point of common coupling. The active power line conditioner system is in compliance with IEEE 519 and IEC 61000-3 recommended harmonic standards. © 2011 IEEE.
Performance analysis of adaptive band hysteresis current controller for shunt active power filter
Prusty S.R., Ram S.K., Subudhi B.D., Mahapatra K.K.
Conference paper, 2011 International Conference on Emerging Trends in Electrical and Computer Technology, ICETECT 2011, 2011, DOI Link
View abstract ⏷
Power Distribution system is polluted by harmonic and reactive power disturbances due to the large usages of non-linear loads (Computers, Laser printers, SMPS, Rectifier etc.). Harmonics cause a number of undesirable effects like heating, equipment damage and Electromagnetic Interference effects in the power system. Active power filter (APF) or Active power line conditioner (APLC) is a suitable solution to compensate for the adverse effects of harmonics and reactive power simultaneously. Synchronous reference frame (SRF) theory is adopted for extracting fundamental components. In this paper, a comparative study of the performances of two current control strategies namely the hysteresis current controller (HCC) and adaptive hysteresis current controller (AHCC) is carried out and superior features of AHCC are established. Results of simulation studies on the performances of HCC and AHCC are included to demonstrate the effectiveness of using adaptive hysteresis band. © 2011 IEEE.
FPGA implementation of digital controller for active power line conditioner using SRF theory
Ram S.K., Prusty S.R., Barik P.K., Mahapatra K.K., Subudhi B.D.
Conference paper, 2011 10th International Conference on Environment and Electrical Engineering, EEEIC.EU 2011 - Conference Proceedings, 2011, DOI Link
View abstract ⏷
A large variety of electronic circuits such as inverter, chopper, cyclo-converters, SMPS used by industrial and domestic purpose, the characteristics of such equipments are non-linear in nature. Due to non-linear characteristics the load current gets distorted which causes undesirable effects like heating, equipment damages, EMI effects etc. in power network. The active power filter (APF) is the best solution for eliminating the harmonics caused by the non-linear loads. This paper presents the implementation of a digitally controlled APF. Designed in Hardware Description Language (VHDL or Verilog) the controller becomes independent of process technology. Synchronous reference frame is used for generation of reference current. PI currents algorithm is written in VHDL code and hysteresis current controller (HCC) together is implemented using FPGA platform. © 2011 IEEE.
