This manuscript examines the implementation of machine learning (ML) algorithms for the detection of muscle activity based on Electromyography (EMG), utilizing Pynq-Z2 to achieve real-time operational efficiency. EMG signals were acquired through an Arduino platform and subsequently processed utilizing the PYNQ-Z2 FPGA board. A total of four ML algorithms, precisely k-Nearest Neighbours (KNN), Decision Trees (DT), Support Vector Machines (SVM), and Random Forest (RF), were implemented to categorize muscle activity attained from the EMG data. The efficacy of each algorithm was assessed concerning classification accuracy, with KNN achieving an accuracy of 97.50%, SVM attaining 98.00%, DT exhibiting a performance rate of 96.00%, and RF producing an accuracy of 95.00%. Feature extraction techniques were employed, specifically the Mean Absolute Value (MAV) as well as the Root Mean Square (RMS), yielding calculated average values of 2.83V and 3.13V, respectively. These findings underscore the viability of integrating Pynq-Z2 with machine learning models to facilitate efficient and precise muscle activity detection, thereby making substantial advancements in real-time, embedded system applications, including wearable health monitoring devices and prosthetic technologies.

The geometric design of electrodes plays a crucial role in determining the biosensor sensitivity and resolution by altering the Electric field (E). Specifically, the value of electric sensing parameters like resistance (R), capacitance (C), and impedance (Z), inherently depends on the strength of the generated electric field between electrodes. So, one must generate a large electric field for the applied AC or DC voltage. Unfortunately, the rigorous practical study on the same is limited on account of cleanroom-based fabrication techniques' cost and time. So, it is essential to study and analyze the geometrical performance of electrodes using simulations - present work aimed at this. In this work, we specifically selected gold-interdigitated microelectrodes (IDμEs) as one of the most viable alternatives to conventional two-electrode systems based on the enhanced field strength (E) generated for the same applied voltage. Specifically, the geometric study of gold IDμEs was carried out using the COMSOL Multiphysics simulator by varying the inter-finger distance and number of fingers between the electrodes. Based on the generated electrical field strength, one can select the best design for biosensor fabrication.

Designing energy-efficient digital FIR filters remains a challenge due to the trade-off between computational accuracy and resource utilization. This study addresses this issue, a novel approach to scheming a highly effective digital Finite Impulse Response (FIR) filter for noise signal and image noise removal applications by integrating an optimized Red Piranha Based Approximate Logarithm Posit Multiplier (RP-ALPM) with a Toffoli-Depth Quantum Adder (TDQA) (DF-TDQA-RP-ALPM) is proposed. The RP-ALPM leverages the accuracy and dynamic range advantages of posit arithmetic while utilizing approximate computing to reduce power and area overheads. The integration of a TDQA ensures efficient quantum operations with minimal depth, enhancing the overall computational efficiency of the FIR filter. Extensive simulations demonstrate significant improvements in power consumption, area, and delay, without compromising filter performance. This work offers a promising solution for energy-efficient digital signal processing in noise reduction for audio and image applications in quantum-inspired computing environments. The proposed DF-TDQA-RP-ALPM filters are intended and implemented in the Verilog programming language, in addition to simulation is on Xilinx ISE 14.5 design tackles. The untried performances of the projected DF-TDQA-RP-ALPM filter are predicted to have a lower delay of 10 ns, and 25.4 mW lower power consumption is associated with the existing filters. The projected Filter is triggered in MATLAB/Simulink for understanding input signals. The experimental performances of the proposed DF-TDQA-RP-ALPM filter are calculated as 85.6 % higher SNR is associated with the standing filters.

Many diseases affect rice crops and cause significant losses in their yield of rice crops. The early detection of these diseases will be beneficial to farmers. Although there are many techniques for diagnosing diseases of rice plants from images, this study focuses on analyzing some of these techniques. This study analyzes not only traditional machine-learning techniques but also a modern approach using cloud software. The study focuses on mainly four types of diseases - namely Bacterial Blight, Blast, BrownSpot and Tungro. These rice diseases lead to the accumulation of toxic metabolites or proteins, and altered hormone levels. This study implemented the techniques and analyzed the methods through various metrics such as accuracy, f1-score, precision. This study performed a comparative study of the aforementioned methods and attempted to determine whether traditional machine-learning techniques or modern cloud-based techniques work better. With a model accuracy of 100%, the proposed method ensures rice nutrient depletion through early detection of rice diseases.

Cloud computing has emerged as a vital platform for processing resource-intensive workloads in smart manufacturing environments, enabling scalable and flexible access to remote data centers over the internet. In these environments, Virtual Machines (VMs) are employed to manage workloads, with their optimal placement on Physical Machines (PMs) being crucial for maximizing resource utilization. However, achieving high resource utilization in cloud data centers remains a challenge due to multiple conflicting objectives, particularly in scenarios involving inter-VM communication dependencies, which are common in smart manufacturing applications. This manuscript presents an AI-driven approach utilizing a modified Multi-Objective Particle Swarm Optimization (MOPSO) algorithm, enhanced with improved mutation and crossover operators, to efficiently place VMs. This approach aims to minimize the impact on networking devices during inter-VM communication while enhancing resource utilization. The proposed algorithm is benchmarked against other multi-objective algorithms, such as Multi-Objective Evolutionary Algorithm with Decomposition (MOEA/D), demonstrating its superiority in optimizing resource allocation in cloud-based environments for smart manufacturing.

Current-mode control is a commonly utilized control strategy for the step-up power converters because these converters' control-to-output transfer function contains right-half plane zeros. The main concern associated with the recent dual-loop current-mode controller (CMC) is that the integrator operates on the error term itself. Thus, integrand can assume extremely large values when error is large such as during transient response, and the controller output may saturate, especially when sufficiently large controller gains are used. If lower gain values of gains are used, the speed of response in the presence of small parameter variations could be much lower. Thus, there is a compromise between the transient response when error signal is large and speed of the response for small error signals. To address these concerns, an improved normalized-error based current-mode controller (NECC) is employed for voltage regulation in a sixth-order boost configuration. This controller's main characteristic is that the integrator now operates on a bounded integrand which is a normalized-error. This avoids the integrator saturation and also increase the room for tuning the controller gains. The state-space averaged model of the topology is given and a detailed stability analysis is shown. The main contribution of the paper is that a detailed comparative study of the traditional CMC and an improved NECC based on some simulation and experimental waveforms is provided. Both simulation and experimental outcomes clearly prove the superiority of the proposed NECC in terms of an improved speed and less overshoot of the output voltage response.

This paper proposes a fourth-order (2-2) switched-current (SI) multistage-noise-shaping (MASH) delta–sigma modulator (DSM) with a simplified digital noise-cancellation circuit (DNCC) by using a Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 µm 1P6M CMOS process. In view of area-efficiency, we propose a small-area current-mode sample-and-hold circuit (S/H) with a modified feedback memory cell (FMC) and cross-connected bias circuit. As a result of modifications to the feedback impedance, the input impedance of the current-mode differential FMC was decreased by [2 + (g0m3/gm1 - 1) × A] times relative to a traditional FMC. Any input current can be processed faster than usual given low input impedance. The MASH architecture inherited a superior signal-to-noise ratio (SNR) due to a simplified DNCC, consisting of six unit-delay circuits using a master–slave D flip-flop (DFF) and a logic circuit using a Karnaugh map. Post-layout simulations reveal that the simulated SNR was 87.1 dB and the effective number of bits (ENOB) was 14.18 bits. Measurements indicated that the SNR was 64.5 dB and the ENOB was 10.42 bits—at a sampling frequency of 10.24 MHz, an oversampling ratio of 256, a signal bandwidth of 20 kHz, and a supply voltage of 1.8 V. The designed chip was measured to have a power consumption of 18.19 mW, a chip area of 0.13 mm2, and a measured figure of merit (FoM) of 331.9 (pJ/conv-step). The advantages of our modulator are its small chip area and high processing speed at all input currents.

This paper proposes a switched-current (SI) sampled and hold circuit (SH) for the 2+2 multi-stage noise shaping (MASH) delta-sigma (ƩΔ) modulator, which is fabricated in TSMC 0.18 μm 1P6 M CMOS process. In the proposed design, the input impedance can be reduced by a factor of (1+A) using the modified feedback memory cell to obtain low transmission error and the circuit stability can be improved with the cross-connected common-mode feedforward circuit (CMFF). A differential cross-connected CMFF circuit can speed up a fast-response circuit and bring a stabilized output current. The proposed digital noise-cancellation circuit not only eliminates the higher-order quantisation noise from the last stage but also cancels the lower-order quantisation noise from the earlier stage of the modulator. The simulation results show that the signal-to-noise and distortion ratio (SNDR) is approximately 87.1 dB, and the effective number of bits (ENOBs) is roughly 14.18 bits at a sampling rate of 10.24 MHz with an oversampling ratio (OSR) of 256 and a signal bandwidth of 20 kHz. The designed chip draws 18.19 mW from the supply voltage of 1.8 V and occupies a core area of 0.13 mm2.

This study focuses on the design of a 2-1 switched-current (SI) multi-stage noise-shaping delta–sigma modulator with a digital noise-cancellation circuit. The noise-cancellation circuit is designed by employing various algorithms for designing the logic circuits and constructing a delay block with an inverter and a transmission gate. It can eliminate the higher-order quantisation noise from the first stage of the modulator completely. In the proposed differential current-mode sample-and-hold circuit, low-input impedance is presented with feedback and width-length adjustment in SI feedback memory cell, a coupled differential replicate with the common-mode feed-forward (CMFF) circuit is used to stabilise the common-mode bias voltage at input terminal, and a differential cross-connected CMFF circuit is utilised to fix the bias voltages. Post-layout simulations reveal that the simulated signal-to-noise-and-distortion ratio (SNDR) was 90.4 dB and the effective number of bit (ENOB) was 14.73 bits. Measurements show that the SNDR was 59.13 dB and the ENOB was 9.53 bits at a sampling rate of 10.24 MHz, an oversampling ratio of 256, and a signal bandwidth of 20 kHz. This design has a power requirement of 12.99 mW from a supply voltage of 1.8 V and occupies a core area of 0.14 mm2

This work presents a one-dimensional magnetic chip composed of a hybrid magnetosensor and a readout circuit, which were fabricated with 0.18 μm 1P6M CMOS technology. The proposed magnetosensor includes a polysilicon cross-shaped Hall plate and two separated metal-oxide semiconductor field-effect transistors (MOSFETs) to sense the magnetic induction perpendicular to the chip surface. The readout circuit, which comprises a current-to-voltage converter, a low-pass filter, and an instrumentation amplifier, is designed to amplify the output Hall voltage with a gain of 43 dB. Furthermore, a SPICE macro model is proposed to predict the sensor's performance in advance and to ensure sufficient comprehension of the magnetic mechanism of the proposed magnetosensor. Both simulated and measured results verify the correctness and flexibility of the proposed SPICE macro model. Measurements reveal that the maximum output Hall voltage VH, the optimum current-related magnetosensitivity SRI, the optimum voltage-related magnetosensitivity SRV, the averaged nonlinearity error NLE, and the relative bias current Ibias are 4.381 mV, 520.5 V/AT, 40.04 V/VT, 7.19%, and 200 μA, respectively, for the proposed 1-D magnetic chip with a readout circuit of 43 dB. The averaged NLE is small at high magnetic inductions of ±30 mT, whereas it is large at low magnetic inductions of ±30 G.

This paper presents a 3-D differential folded Hall sensor (HS) fabricated using standard 0.18-ìm CMOS technology; this HS includes 1-D folded lateral Hall sensor (FLHS) and 2-D folded vertical Hall sensor (FVHS). The proposed 3-D HS is laterally folded to reduce the effective conduction length and to decrease the offset voltage; a p+ guard ring is used to narrow the conducting channel and to improve magnetosensitivity. The magnetosensitivity is improved two-fold and the offset is eliminated using the differential topology. The proposed 1-D FLHS is sensitive to magnetic induction perpendicular to the chip plane BZ through the fast accumulation-slow release mechanism; the proposed 2-D FVHS is responsive to magnetic induction parallel to the chip plane, BX and BY, based on the interaction between the magnetoresistor (MR) and magnetotransistor, where MR is more dominant. Notably, the proposed 3-D HS operates with a small offset voltage of 0.26 mV and without magnetic hysteresis. For 2-D FVHS, at a voltage gain of 89.6 dB, the maximum sensor output ΔVH is approximately 196.4 mV at the applied magnetic induction of 5 mT and the maximum supply-current-related sensitivity SRI is approximately 5943 V/A·T at a current consumption of 6.25 mA for x- or y-channel. For 1-D FLHS, the maximum ΔVH is approximately 470.8 mV at 5 mT and the maximum SRI is approximately 14790 V/A·T at a bias current of 6.25 mA for z-channel. The magntosensitivity SRI of 1-D FLHS is approximately 2.35 times that of 2-D FVHS. The designed 1-D FLHS is a comparable to the performance of other publications. However, it experiences a high nonlinearity error in output Hall voltage at a low bias current. By contrast, the proposed 1-D FLHS has a linear performance in output Hall voltage at a high bias current.

This paper focused on the design of a 2+1- order Switched-current MASH Delta-Sigma ADC with the digital cancellation circuit in TSMC 0.18-μm 1P6M CMOS process. To combat errors in MASH architectures, we have to cancel the errors by utilizing a pertinent digital cancellation circuit; the output of digital code contains the numbers and position of characteristics to the latter part of the digital filter to facilitate the processing. We proposed an algorithm for the logic circuit and employed simplified delay block in digital cancellation circuit to cancel the noise errors from the earlier stage, and to generate a third-order noise shaping output. Our simulation results show that signal-To-noise and distortion ratio (SNDR) is 90.4 dB, and the effective number of bits (ENOB) is 14.73 bits at a sampling rate of 10.24 MHz with an oversampling ratio (OSR) of 256, and the signal bandwidth is 20 kHz. This design draws 12.99 mWfrom the supply voltage of 1.8V and occupies a core area of 0.14 mm2.

This paper presents the design and implementation of the differential Dickson voltage multiplier with a matching network which is used in the radio frequency (RF) energy harvester at GSM frequency band. The proposed RF energy harvester consists of a matching network and a Dickson rectifier. Those circuits are designed and simulated with standard TSMC 0.18 μm 1P6M CMOS process. The matching network is used not only to obtain the maximum power deliver from antenna to the RF-DC rectifier, but also to have the maximum conversion efficiency. In the proposed differential Dickson voltage multiplier, a native MOSFET is considered in implementing the multiplier with low threshold voltage, and a modified Dickson voltage multiplier with differential schematic is used to enhance the performance of the Dickson voltage multiplier. According to the simulated results, the conversion efficiency, input return loss, and output voltage are 28.83%,-47.285 dB, and 1.5 V, respectively, at a load impedance of 239 kΩ, an input power of-10 dBm, and in GSM frequency band.

This work develops a third-order multibit switchedcurrent (SI) delta-sigma modulator (DSM) with a four-bit switchedcapacitor (SC) flash analog-to-digital converter (ADC) and an incremental data weighted averaging circuit (IDWA), which is fabricated using 0.18μm 1P6M CMOS technology. In the proposed DSM, a 4-bit SC flash ADC is used to improve its resolution, and an IDWA is used to reduce the nonlinearity of digital-to-analog converter (DAC) by moving the quantization noise out of the signal band by first-order noise shaping. Additionally, the proposed differential sample-and-hold circuit (SH) exhibits low input impedance with feedback and width-length adjustment in the SI feedback memory cell (FMC) to increase the conversion rate. A coupled differential replicate (CDR) common-mode feedforward circuit (CMFF) is used to compensate for the mirror error that is caused by the current mirror. Measurements indicate that the signal-to-noise ratio (SNR), dynamic range (DR), effective number of bits (ENOB), power consumption, and chip area are 64.1 dB, 64.4 dB, 10.36 bits, 18.82 mW, and 0.45 × 0.67 mm2 (without I/O pad), respectively, with a bandwidth of 20 kHz, an oversampling ratio (OSR) of 256, a sampling frequency of 10.24 MHz, and a supply voltage of 1.8 V.

In this article, an encryption algorithm with an error detection technique is presented for highly secured reliable data transmission over unreliable communication channels. In this algorithm, an input data is mapped into orthogonal code first. After that the code is encrypted with the help of Linear Feedback Shift Register (LFSR). The technique has been successfully verified and synthesized using Xilinx by Spartan-3E FPGA. The results show that the error detection rate has been increased to 100% by proposed encryption scheme is effective and improves bandwidth efficiency.

Three-dimensional integration suffers from heat dissipation between the layers due to the power consumed by various resources. In this paper, we show the significance of distribution of power density among the layers of a three-dimensional integrated circuit structure which can reduce the overall chip temperature as well as the peak temperature. Our experiments are developed using industry standard ANSYS tool and academic research tool HOTSPOT. Through the results obtained in this paper, we recommend that effective power density distribution at the early stage of design cycle, especially in the partitioning stage, will help in optimizing chip temperature and thus can reduce the burden on later stages of design cycle for handling critical design metrics.