Real-time low-light image enhancement has several potential applications, such as advanced driver assistance systems (ADAS), remote sensing, object tracking, etc. The Retinex-based algorithms are mostly used to restore the visibility of low-light images. However, they perform complex mathematical operations over a large spatial window. Consequently, their hardware realization is tedious, and few researchers have attempted to address this problem. In this brief, we propose a Retinex-based algorithm that employs a low-cost edge-preserving filter for illumination estimation. Although certain approximations are used to curtail the hardware logic resource requirement, the quality of the enhanced image is not compromised. The proposed architecture requires only 10868 LUTs and 7409 registers when implemented on ZynQ 7 FPGA. Moreover, it can process HD images (1920× 1080 ) at the rate of 60 frames per second (fps).

Low lighting conditions degrade the quality of the captured image by darkening some of its parts. This may lead to the loss of important information contained in the captured image in low-light. It is always desirable to improve the visual quality of low-light images. In this paper, a low-light image enhancement model based on the dehazing principle is proposed to address this issue. Further, its hardware architecture is proposed to meet the real-time system requirement. The proposed pixel-based non-linear transmission estimation technique prevent images from being over-enhanced. Additionally, it suppresses the artifacts around the edges. This curtails the need for an edge-preserving filter. The field-programmable gate array (FPGA) implementation of the proposed architecture requires only 694 LUTs, and it is capable of processing more than 60 images of resolution 1920× 1080 per second.

Hazy weather degrades the vividness of the images captured by real-time systems for applications such as object detection, remote sensing, and surveillance systems. This affects the performance of such real-time systems. The hardware implementation of a real-time haze removal system is imperative to solve these problems. Such a solution is proposed in this article. Here, the saturation-based hardware implementation of an image dehazing system is presented. To estimate atmospheric light more precisely, a 15 × 15 window minimum filter is implemented, which uses the downsampled hazy image to estimate the atmospheric light. Furthermore, we have employed saturation-based transmission map estimation, which makes our approach pixel-based rather than patch-based. Unlike existing patch-based methods, the proposed method requires neither an edge detection unit nor an image filtering unit to suppress halo artifacts around edges. The VLSI architecture of the proposed dehazing system comprises seven pipelined stages. It is implemented on FPGA as well as ASIC (65-nm technology node) platforms. The ASIC implementation of the proposed dehazing system yielded a maximum throughput of 624 Mpixels/s, which is fast enough to process 3840 × 2160 resolution at a rate higher than 70 fps with only 13.2k logic gates count.

Image dehazing performs a crucial role in various real-time applications such as remote sensing, Advance Driver Assistance System (ADAS), surveillance systems etc. Therefore, a hardware implementation of an image dehazing system with high efficiency and low hardware cost is very much desirable. In this paper, we have proposed a nine-stage pipelined hardware architecture for haze removal which uses saturation information of the hazy image as the basis to derive local airlight (atmospheric light) and transmission of the individual pixels of the dehazed image. Since we have used pixel-based approach, our method does not require any edge detection unit as in the patch-based approach to decide the pixel in a patch is on the edge or not. The proposed method can operate at 94.7 MHz and require 970 logic elements (LEs) when implemented on the FPGA platform.

Low power consumption of electronic devices has become one of the most desirable factors in the present day’s technology. Static random access memory (SRAM) being an integral part of most of the electronic gadget suffers from leakage current which results in static power dissipation and subsequently affects its performance particularly during standby or hold mode. This becomes crucial especially for those systems which are portable and have limited power supply. This work therefore proposes a body bias controller implemented with a 7T SRAM cell at 28 nm CMOS technology node which lowers the static power consumption and increases the hold static noise margin (HSNM) of SRAM during standby mode by changing the threshold voltage. Moreover, it also reduces write delay due to reduction in threshold voltage of proposed design without having a significant effect on write static noise margin and read static noise margin. It has been noticed that there is a reduction of 40%, 28%, 41.9% and 30% in static power dissipation whereas there is an enhancement of 19%, 14.2%, 6.6% and 5.2% in HSNM of the proposed design when compared to 6T SRAM cell, 7T SRAM cell, WRE8T SRAM cell and 9T SRAM cell, respectively. The proposed design can thus be a suitable alternative for low power SRAMs.