An Arbiter PUF (APUF) is a useful hardware security primitive. However, FPGA-based design and implementation of APUF circuits with superior values of quality metrics have proven to be extremely challenging. In this work, we have designed a novel 64-bit APUF which is "robust-by-construction", i.e., it has close to ideal values of quality metrics when implemented. The circuit structure and methodical implementation on a Xilinx FPGA platform ensure that the response bit is unbiased, and is dependent on intrinsic process variation alone. The effect of placement and routing tools and the choice of last-stage arbiters have been investigated in detail. Our implemented APUF achieves average Uniformity, Uniqueness, Steadiness, Min-Entropy, and Reliability (evaluated at four operating temperatures) metric values of 51.22%, 50.81%, 1.82%, 88.38%, and 99.34%, respectively. A software-based fuzzy error correction scheme is used on the responses generated at different temperatures. The design is also found to be strongly resistant to machine learning based model-building attacks, with Logistic Regression (LR) and Support Vector Machine (SVM) prediction accuracies of 51.22% and 52.61% respectively, on a dataset of 2,097,152 CRPs using additive delay models and a security analysis is performed using MLP modelling-attacks of the pypuf framework.

Uniqueness and Uniformity are two important quality metrics that determine the practical usability of a strong Physically Unclonable Function (“strong PUF”) instance, or an ensemble of strong PUF instances. In this paper, we consider the strong PUF instance as a Boolean function, and theoretically enumerate the total number of usable single-output practical strong PUF instances, assuming commonly acceptable thresholds of the Uniqueness and Uniformity metrics. We have computed the number of possible strong PUF instances with ideal Uniformity (= 0.50), and Uniformity within an acceptable range of the ideal value, and the same for Uniqueness. Additionally, given an ideal Uniformity, we have enumerated the number of strong PUF instances with ideal Uniqueness (= 0.50), and Uniqueness within an acceptable range. Our analysis is completely generic and applicable to any PUF variant, independent of its structure and operating principle.

Physical Unclonable Functions (PUFs) are vulnerable to various modelling attacks. The chaotic behaviour of oscillating systems can be leveraged to improve their security against these attacks. We have integrated an Arbiter PUF implemented on a FPGA with Chua's oscillator circuit to obtain robust final responses. These responses are tested against conventional Machine Learning and Deep Learning attacks for verifying security of the design. It has been found that such a design is robust with prediction accuracy of nearly 50%. Moreover, the quality of the PUF architecture is evaluated for uniformity and uniqueness metrics and Monte Carlo analysis at varying temperatures is performed for determining reliability.