Network-on-Chip (NoC) is the state of the art on-chip interconnection network for packet based communication. NoCs can offer low packet latency, high bandwidth, high throughput with minimum area, better energy efficiency and fault tolerance. Routers are the basic building blocks of the NoCs. In this paper, we present the design of a Congestion Aware Router for NoC which is then implemented using Vivado HLS. The router is then used to develop a scalable NoC based on mesh topology. Using the NoC as a test bed we carry out simulations and estimate performance metrics like latency, waiting time and total packets handled for various configurations of NoC. Provisions to alter parameters like buffer depth, packet size, packet injection interval and traffic are also added. Further, we propose a simple mechanism for detecting congestion at the router. The congestion metric is then used to adapt the XY dimension order routing into a Congestion Aware minimal adaptive X/Y routing strategy with very low hardware overhead. The proposed routing method is compared against conventional XY DOR, GCA routing and RCS based routing algorithms for different parameter variations. The results show that the proposed routing method can reduce packet latency for different traffic patterns at medium packet injection rates.

The trend towards multi-core and many-core processors has changed the landscape of computers and servers. Now the performance of a microprocessor heavily depends not only on the data path but also on the memory technology and communication technology. On-chip communication networks or Network-on-Chip is a component which facilitates communication between the cores of a microprocessor. In this manuscript we propose an analytical model for the analysis of Network-on-Chip performance based on Jackson queuing networks for applications that exhibit Poisson injection process. The injection process statistics and the traffic profile of PARSEC benchmarks have been characterized. We have shown that injection process of PARSEC benchmarks does not match with the well known probability distributions using Quantile-Quantile plot and Kolmogorov-Smirnov test. For realistic benchmarks that does not follow Poisson injection process we propose G/D/1 queuing model for the NoC router. We have carried out performance analysis using the traffic characterization in conjunction with our analytical model for prediction of performance metrics. The analytical model offers a speed up of around 13 times in comparison with the simulation based performance evaluation. The percentage of error between the analytical model and simulation is less than 6% for most of the benchmarks except Canneal and Ferret. We have also compared our analytical model results with the results of SNIPER simulator.

In a multi-core general purpose processor or System-on-Chip, interconnection network plays a very important role. An on-chip interconnection network or Network-on-Chip may be designed to achieve maximum throughput or minimum latency depending on the type of application to be run on the processor. In this paper we present an analysis of effect of different parameters like network size, routing, traffic patterns, flit size, buffer size on power consumption of the Network-on-Chip. We also discuss the trade-offs between power, throughput, and delay metrics for an efficient network operation. Our analysis will help in designing new routing algorithms, allocation algorithms for Network-on-Chip.

This work discusses the availability of cache memories for VoD service in Time and Wavelength Division Multiplexed Passive Optical Network (TWDM PON) ring topology. In a unidirectional ring topology with TWDM PON, the wavelength channels are enabled in an anti-cyclic manner through intermediate devices such as Remote Node (RN) and splitter as per traffic requirements. The provision of cache storage at subsystems of ring topology, namely, Optical Line Terminal (OLT), RN, and Optical Network Unit (ONU) enables the users to access the VoD service within reach rather than from a typical video server. Thus, this mechanism reduces the delay as well as power requirements. However, in this paper the analytical emphasis on the ring topology is confined only to power requirements through two situational cases. In the first case, the cache storage at OLT and ONU is only availed. While in the second case, the cache available at RN was also made to use. It is observed that the power consumption in the second case is lesser than in the first case. Due to more decentralization of cache availability in the second case, relatively 70 % more power savings are observed.

Network-on-Chip is responsible for on-chip communication in multi-core and many-core processors. A Network-on-chip is composed of several routers and channels, each router working on behalf of a processor core or main memory. Buffers, switches, arbiters and allocators are some of the components inside the router of an on-chip network. Along with latency and throughput, power consumed by the interconnection network is a crucial factor to estimate the performance of a processor. In this paper we present a review of power consumption of Network-on-Chip router and its internal components. The majority of the power consumed by a Network-on-Chip router is consumed by the buffers.

Network-on-chip (NoC) is an integral part of many-core microprocessors. Performance analysis of network-on-chip directly affects the performance of the microprocessor. In this paper we propose a mathematical model to represent packet flow in an NoC as an open feed-forward queuing network. We study the performance of NoC by varying different parameters that includes packet injection rate, packet size, buffer size and number of virtual channels. We also discuss how different flow control algorithms, injection processes, traffic patterns can be incorporated in our model. Apart from the speedup achieved by our model, we also demonstrate that our model can be used to explore various configurations of NoC with minimal error.

In a distribution system, load and distributed generation connected to a feeder are subject to uncertainty. Conventional capacitor placement and sizing methods do not consider uncertainty in power injections, due to which the results may be erroneous. In literature, affine arithmetic (AA) is one of the tools used for incorporating uncertainty in power system analysis. However, conventional division operation in AA gives rise to extra noise terms in the resulting affine form, which are not due to the actual uncertainty sources but are due to the nonaffine operations. The present work incorporates modified AA division which does not generate any additional noises, thereby improving the accuracy. Buses in the distribution network are ranked in decreasing order of rate of change of active power loss in line with respect to the change in the effective reactive power flow in that line. The top three ranked buses are chosen as candidate buses for capacitor connection. The required affine reactive current injection at the candidate buses is calculated, and the corresponding affine capacitive kVAR required is obtained through modified AA-based backward/forward sweep (BFS) power flow analysis. The intervals for the cost incurred in losses, voltage profiles with and without capacitor are calculated, and savings for capacitor connected system is calculated. Switchable capacitors are used for reactive power injection. The proposed method is tested on 15, 33 and 118 bus radial distribution systems. The results show that the proposed modified AA method is accurate than existing interval arithmetic-based method.

The hardware realization of fast fourier transform (FFT) consists of complex arithmetic operations such as multiply and accumulate. The key idea of this paper is to implement the 8-point Radix-2 DIT (Decimation In Time) FFT. In the FFT algroithm the twiddle factor generation by traditional method of generating sine and cos is replaced by the CORDIC algorithm for trigonometric functions. For the multiply and accumulate unit, different multipliers were used namely CORDIC multiplier, Single precision floating point multiplier. The adder blocks used in the implementation are linear adders such as Ripple Carry Adder (RCA) and parallel prefix adders such as Kogge-Stone Adder (KSA). Different combinations of multipliers and adders are used in the implementation of FFT, using VHDL in VIVADO 2016.2 version and programmed it in Xilinx ZYNQ FPGA board. The FFT implementation using single precision floating point multiplier incorporated with CORDIC multiplier and koggestone adder gives better delay performance compared to other combinations. In terms of area the combination of CORDIC multiplier with Ripple carry adder performs best.

Synchronous DRAM (SDRAM) has become memory of choice for desktop computers, laptops and embedded systems due to its significant features like high speed, burst access..etc. As SDRAM has many phases of operation like write phase, burst phase, active phase, precharge phase there is need for a memory controller to manage the memory. The main purpose of the SDRAM controller is to refresh the SDRAM cells periodically and control the flow of data to/from SDRAM. Efficient design and verification of the SDRAM controller is required to minimize the memory access latency and ensure the correct operation of SDRAM. In this paper we have verified the SDRAM controller using SystemVerilog test bench architecture. Our model has verified the SDRAM controller against most of the test cases provided by the specification sheet and also achieved 100 percent code coverage. The design was verified using Modelsim SE-64 10.5.

Network-on-Chip (NoC) is the communication backbone of multi-core and many-core processor architectures. Wormhole flow control is the commonly used flow control mechanism in on-chip interconnection networks, however it causes head-of-line blocking as network load increases which can be solved using virtual channel flow control. In this paper we investigate the effect of Virtual Channels (VC) on the performance of NoC by varying injection rate, traffic pattern and the packet length. We simulate an 8×8 mesh network with dimension order routing. Synthetic workloads are used to find the effect of virtual channels on throughput and latency. We show that as the number of virtual channels is increased there is an improvement in the throughput and latency of the network up to a certain number of virtual channels beyond which the network reaches saturated state. Our work can be used as a guidance to find the optimal number of virtual channels for a given NoC configuration and traffic parameters.