Resource-constrained Internet of Things (IoT) edge devices demand lightweight, energy efficient, and secure cipher designs with CMOS technology scaling to enhance hardware security. This work proposes and demonstrates for the first time the potential and challenges of using NCFETs for energy efficient and secure S-box design used in lightweight ciphers exploring the Feistel network structure at VDD = 0.5 V. Performance benchmarking is performed for the proposed NCFET-based S-box design of a Feistel network SLIM cipher with a baseline CMOS SLIM cipher and other existing NCFET PRESENT Cipher with Substitution and Permutation (SPN) networks. The proposed NCFET S-box design exploits the unique steep slope device characteristics and increases non-linearity in power traces caused by the extra gate capacitance of the NCFETs along with the highly secure Feistel network structure to enhance overall energy efficiency and DPA attack resiliency. A thorough DPA resiliency analysis of the proposed S-box design with performance metrics such as SNR, MTD, and SPD performance comparison with the baseline CMOS design and other state-of-the-art S-box designs has been performed. Performance benchmarking of the proposed S-box design of an ultra-lightweight NCFET-based SLIM cipher design with an equivalent baseline CMOS design shows ~4.25× lower energy consumption, a 16× increase in the attacker effect ratio, a ~3.7× reduction in signal-to-noise ratio (SNR) values, a 16× increase in the minimum traces to disclosure (MTD) value, and a ~13.4× higher security power delay (SPD) value at VDD = 0.5 V.

A Negative Capacitance Field effet transistor (NCFET) based Dual split control (DSC) 6T-SRAM cell has been designed and explored with Computing-in memory (CiM) architecture for energy efficient demonstration of Deep neural networks (DNN) basic operation such as Input-Weight (Dot) Product. The impact of ferro electric layer thickness (T fe ) on the SRAM cell perfomance metrics such as read noise margin (RNM), write noise margin (WNM) and energy efficiency for read and write operations have been analyzed at supply voltages of 0.3 V and 0.5 V. It has been observed that due to the steep slope characteristics, the NCFET based DSC 6T-SRAM cell design exhibits better RM, WM, and energy efficiency as compared to the baseline CMOS DSC SRAM cell design at V DD  = 0.3 V and 0.5 V respectively (with T fe range of 1 nm to 3 nm). Further, NCFET dual split control scheme for 6T-SRAM cell demonstrate improved read stability and write ability when compared with NCFET 6 T-SRAM cell design along with improved energy efficiency. NCFET based DSC 6T-SRAM CiM cell design has ?22.77× and 12.41× lower energy consumption compared to the équivalent baseline 40 nm CMOS/baseline SRAM CiM design and ? 25.80× and 22.76× lower energy consumption compared to the NCFET based SRAM CiM at V DD  = 0.3 V and 0.5 V respectively. NCFETs have improved steep subthreshold slope characteristics at an optimal T fe value and NCFET SRAM based CiM circuits are expected to have higher noise margins and lower energy consumption compared to the baseline CMOS designs and are effective for NCFET based computing in-memory architectures with reduced read disturb issues in combination with DSC concept.

Computing in-memory (CiM) is an alternative to von-Neumann architectures for energy efficient AI edge computing architectures with CMOS scaling. Approximate computing in-memory (ACiM) techniques have also been recently proposed to further increase the energy efficiency of such architectures. In the first part of the work, a negative capacitance FET (NCFET) based 6T-SRAM CiM accurate full adder has been proposed, designed and performance benchmarked with equivalent baseline 40 nm CMOS design. Due to the steep slope characteristics of NCFET, at an increased ferroelectric layer thickness, T of 3 nm, the energy consumption of the proposed accurate NCFET based CiM design is ?82.48% lower in comparison to the conventional/Non CiM full adder design and ?85.27% lower energy consumption in comparison to the equivalent baseline CMOS CiM accurate full adder design at V = 0.5 V. This work further proposes a reconfigurable computing in-memory NCFET 6T-SRAM full adder design (the design which can operate both in accurate and approximate modes of operation). NCFET 6T-SRAM reconfigurable full adder design in accurate mode has ?4.19x lower energy consumption and ?4.47x lower energy consumption in approximation mode when compared to the baseline 40 nm CMOS design at V = 0.5 V, making NCFET based approximate CiM adder designs preferable for energy efficient AI edge CiM based computing architectures for DNN processing.

Cataracts, known for lens clouding and being a common cause of visual impairment, persist as a primary contributor to vision loss and blindness, presenting notable diagnostic and prognostic challenges. This work presents a novel framework called the Cataract States Detection Network (CSDNet), which utilizes deep learning methods to improve the detection of cataract states. The aim is to create a framework that is more lightweight and adaptable for use in environments or devices with limited memory or storage capacity. This involves reducing the number of trainable parameters while still allowing for effective learning of representations from data. Additionally, the framework is designed to be suitable for real-time or near-real-time applications where rapid inference is essential. This study utilizes cataract and normal images from the Ocular Disease Intelligent Recognition (ODIR) database. The suggested model employs smaller kernels, fewer training parameters, and layers to efficiently decrease the number of trainable parameters, thereby lowering computational costs and average running time compared to other pre-trained models such as VGG19, ResNet50, DenseNet201, MIRNet, Inception V3, Xception, and Efficient net B0. The experimental results illustrate that the proposed approach achieves a binary classification accuracy of 97.24% (normal or cataract) and an average cataract state detection accuracy of 98.17% (normal, grade 1—minimal cloudiness, grade 2—immature cataract, grade 3—mature cataract, and grade 4—hyper mature cataract), competing with state-of-the-art cataract detection methods. The resulting model is lightweight at 17 MB and has fewer trainable parameters (175, 617), making it suitable for deployment in environments or devices with constrained memory or storage capacity. With a runtime of 212 ms, it is well-suited for real-time or near-real-time applications requiring rapid inference.

Maintaining quality control is of utmost importance in the manufacturing industry, particularly when it comes to small electronic devices that heavily depends on printed circuit boards (PCBs). Detection of defects throughout the production process is extremely difficult. However, the incomplete labelling of PCB defect datasets makes it harder to understand models and reduces their precision. To address this issue, this study introduced a novel ROI-based PCB defect dataset that provides comprehensive labeling for all defect classes. To evaluate the effectiveness of the proposed dataset, we employed lightweight object identification model was YOLOv7. This model was designed specifically for efficient and accurate recognition and classification tasks. The quantitative results demonstrate that, when coupled with lightweight deep learning model, with the proposed dataset outperforms existing datasets. This study makes a substantial contribution to addressing the issues related to PCB defect datasets and provides information regarding the efficiency of lightweight object identification algorithms for defect detection tasks.

In the domain of printed circuit board (PCB) defect detection and classification, the availability of diverse and comprehensive datasets is fundamental for developing effective detection models. However, existing datasets often lack comprehensive labeling and focus on specific defect types, limiting their applicability to real-world scenarios. To address this gap, we introduce a new dataset named ‘dataset for Mixed Defect Detection in PCB’ (MDD_PCB), which includes intentionally induced mixed PCB defects to provide a more realistic representation of practical scenarios. We evaluate the MDD_PCB dataset using YOLO models and implement it successfully for real-time inference on Jetson Nano, achieving enhanced detection capabilities. Our optimized YOLOv5n model trained on the MDD_PCB dataset achieves impressive metrics (accuracy 93%, precision 95%, recall 96%, mAP 95%, F1-score 94%) with a detection speed of 120.69 frames per second (FPS). Real-time deployment on the Jetson Nano demonstrates practical usability with a detection speed of 30 frames per second (FPS). These results underscore the significance of the diverse dataset proposed, which contributes to robust detection solutions and advances in PCB defect detection methodologies. © 2024 The Authors.

Recent hardware developments in artificial intelligence (AI) edge devices expect architectures to support multiply and accumulation operations while preserving high inference accuracy and energy efficiency. This work proposes a compute in-memory (CiM) cell design with steep slope Negative capacitance field effect transistors (NCFET) for energy efficient computing architectures. The NCFET based 8T SRAM cell has been designed and analyzed for performance metrics such as noise margins and energy consumption during read/write modes for an optimum Ferroelectric layer thickness (Tfe) at VDD=0.3 V and 0.5V. Further, the NCFET 8T SRAM cell has been modified to realize energy efficient operations such as NCFET CiM based 2-input AND gate, NCFET CiM based 2-input XOR gate and NCFET CiM based half adder. Proposed NCFET CiM AND logic design exhibit ~5.85x lower energy consumption, NCFET CiM XOR logic design has ~3.29x lower energy consumption and NCFET CiM half adder logic design has ~6.57x lower energy consumption in comparison to equivalent baseline 40nm CMOS designs at VDD=0.5V. © 2024 IEEE.

The paper provides a comprehensive comparison of differential amplifiers designed with CMOS (Complementary Metal-Oxide-Semiconductor) at the 45nm technology node and NCFET (Negative Capacitance Field-Effect Transistor) at the 40nm technology node. With the ongoing advancements in semiconductor technologies, the investigation of innovative transistor structures like NCFETs has become essential due to their potential for improved performance and reduced energy consumption compared to conventional CMOS devices. The performance of CMOS and NCFET-based differential amplifiers is evaluated based on various key parameters, including AC Gain (dB), Phase Margin (degree), Unity gain bandwidth (Hertz), Bandwidth (Hertz), delay (nano seconds), Common-Mode Rejection Ratio (CMRR in dB), Input Common-Mode Range (ICMR+ and ICMR- in volts), Slew Rate (Volts/microseconds), Power Consumption (micro-Watts), and Power Supply Rejection Ratio (PSRR in dB). Significant differences in performance metrics between CMOS and NCFET-based designs are identified and analyzed.

Energy-efficient and secure cipher design for resource constrained IoT applications is a pressing challenge with CMOS technology scaling and increased hardware attacks. This work presents the potential and design challenges exploring Negative Capacitance FETs (NCFETs) for energy efficient and differential power analysis (DPA) attack resilient circuit/cipher design at scaled supply voltages. Design and performance benchmarking of one such ultra-light weight block cipher, i.e. PRESENT-80 exploring 40 nm NCFET device technology is demonstrated and evaluated resiliency against DPA attack for the first time. 40 nm NCFETs show optimum device performance with a ferroelectric layer thickness (tfe) in the range of 3 nm–5 nm. NCFET with tfe of 5 nm shows ?15.7 × higher ON current, 1.77 lower leakage current and subthreshold swing of 49mV/dec compared to the baseline CMOS device. NCFET based PRESENT-80 block cipher design achieves ?3.2 × lower energy consumption compared to the baseline equivalent 40 nm CMOS design under similar design constraints. NCFET PRESENT-80 cipher design is evaluated against DPA attack and results indicate NCFET based cipher design to be highly resilient compared to the baseline CMOS design. With the non-linearity in power traces caused by the additional capacitance of NCFET device structure, the proposed NCFET PRESENT cipher design achieves ?4 × increased attacker effort ratio and low Signal-to-noise ratio (SNR) values compared to the equivalent baseline CMOS design.

An Energy-Efficient Computing-in-Memory (CiM) cell design utilizing a Negative Capacitance (NC) FET has been proposed to support computing architectures for Deep Neural Networks (DNNs). The NCFET device characteristics for CiM architectures have been studied to determine an optimal device performance window by changing the thickness of ferroelectric layer (T fe ). The performance metrics such as read margin (RM), write margin (WM), read energy and write energy of NCFET 6 T SRAM cell are analyzed with varying T fe at two different supply voltages 0.3 V and 0.5 V respectively. NCFET based SRAM cell design achieves higher RM and WM at T fe of 3 nm and lower energy consumption at 1 nm T fe as compared with the baseline SRAM cell design at both V DD  = 0.3 V and V DD  = 0.5 V respectively. 6 T NCFET based CiM cell design for performing basic input-weight product operation (IWP) has been demonstrated and performance comparison is done with baseline CMOS design at V DD  = 0.3 V and V DD  = 0.5 V. In comparison with the baseline CMOS CiM cell design, NCFET based SRAM CiM design achieves ?2.59x and 1.62x lower energy consumption at V DD  = 0.3 V and V DD  = 0.5 V respectively with an optimal T fe window of 1–3 nm.

Approximate arithmetic computing circuits and architectures have been proven to be energy efficient designs for Deep Neural Networks (DNNs) which are error resilient. In this paper, an approximate 8-bit Wallace Multiplier has been proposed and designed in 90nm CMOS technology for energy efficiency. The proposed 8-bit approximate multiplier design consumes ~32% less energy in comparison to an accurate 8-bit Wallace Tree multiplier with less than 20% Mean Relative Error (MRE).

Negative capacitance Field Effect Transistor (NCFET) is a promising CMOS compatible technology that exhibits relatively lower subthreshold swing (SS) and higher ON current at scaled VDD. This paper for the first time exploresthe design and security evaluation of NCFET based ultra- light weight PRESENT-80 cipher at 0.5V VDD. The NCFET based PRSESNT-80 cipher is analyzed by varying the ferroelectric thickness (tfe) of NCFET device. NCFET basedPRESENT-80 exhibit energy efficiency at tfe of 4nm. At 0.5V, NCFET based PRESENT-80 at tfe of 4nm exhibits 3.2× lower energy consumption compared to baseline 40nm CMOS design with 100MHz operating frequency. Apart from this, the security of NCFET based PRESENT-80 is evaluated against differential power analysis (DPA). With non-linear variation of dynamic power consumption profile, NCFET based PRESENT-80 is proved to be resilient against DPA compared to the baseline MOSFET design.

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The Multiply Accumulate Unit, which is utilized to boost the processor's overall speed, is the subject of this essay. Applications for digital signal processing that use multiply-accumulate units include convolution, digital filters, image, video, and audio, among others. Accuracy is not given priority when image and video processing applications are taken into account, hence an approximate multiply-accumulate unit is built. This approximate multiply-accumulate unit, compared to a floating point multiply-accumulate unit simulated in Xilinx ISE 14.5, and various parameters like area, delay, and speed are compared between floating and approximate MAC consisting of an approximate multiplier efficient, an approximate adder, and an approximate accumulator. The approximate multiply-accumulate unit uses less space (66% less) and has a 75% shorter delay, all of which contribute to its high speed.

A Negative capacitance field effect transistor (NCFET) based 6T SRAM based Computing-in memory (CIM) cell has been designed and explored for energy efficient demonstration of basic Deep neural networks (DNN) operation such as XNOR or Input and Weight product operation. The characteristics of NCFET devices have been explored to determine the optimal device performance window by varying the ferroelectric layer thickness of the device (Tfe) and it has been observed that the 40nm NCFET with a Tfe of lnm exhibits approximately 1.64x higher ON current, 1.1x lower leakage current and a Subthreshold swing of below 50mV/dec compared to the baseline MOSFET. Furthermore, NCFET based 6T SRAM CIM cell has been designed to perform basic XNOR operation at VDD = 0.3V and 0.5V. NCFET based CIM XNOR design has approximately 2.6x and 1.6x lower energy consumption compared to the equivalent baseline 40nm CMOS design at VDD = 0.3V and 0.5V respectively.

Neural networks are a set of algorithms modeled on the human brain, primarily for pattern recognition which has a special category called convolutional neural networks. Convolutional neural networks also called as ConvNets or CNNs which is the most important tool for the machine learning practitioners today. CNN has proved that its works effectively in various areas such as recognition of image and classification. This CNNs also have been proved successful in identifying objects and faces and identifying traffic lights apart from powering vision in robots and self-driving cars. Among these layers hidden layer plays an important role which inturn consists of convolution, Activation Filter (ReLU) and pooling. Any CNN which is used in identifying image or classifying an object etc., must contain these blocks to work efficiently for classification of the higher representation of the image content. The primary contribution of this work is a step towards assisting an introductory designer targeting to design and implement a basic CNN in FPGA and detailed design procedure and steps are outlined in the paper. Basic CNN by taking 5*5 input feature is designed in Xilinx Vivado and parameters such as area, delay and speed are compared.

Present complementary metal–oxide–semiconductor (CMOS) technology with scaled channel lengths exhibits higher energy consumption in designing secure electronic circuits against hardware vulnerabilities and breaches. Specifically, CMOS sense amplifier-based secure differential power analysis (DPA) countermeasures at scaled channel lengths show large energy consumption, with increased vulnerability. Additionally, spin-transfer torque magnetic tunnel junction (STT-MTJ) and CMOS-based logic-in-memory (LiM) cells demonstrate high energy consumption due to the large write current requirement of the STT-MTJ and poor MOS device performance at scaled channel lengths. This paper for the first time leverages emerging tunnel field effect transistor (TFET) steep-slope device characteristics and compatible non-volatile STT-MTJ devices for enhanced hardware security with ultra-low energy consumption at lower supply voltages. TFET-based sense amplifier-based logic (SABL) gates are proposed that achieve 3× lower energy consumption than the Si FinFET SABL designs. Further, utilizing TFET SABL gates, a TFET PRIDE S-box is designed that exhibits higher DPA resilience with 3.2× lower energy consumption than the FinFET designs. With the resulting lower static power consumption, TFET SABL-based cryptosystems are thus less vulnerable to static power side-channel attacks. Additionally, the proposed STT-MTJ and TFET LiM gates achieve 4× lower energy consumption than the STT-MTJ and FinFET designs. Lastly, these gates are explored in a logic encryption/locking technique that shows 3.1× lower energy consumption than the STT-MTJ and FinFET-based design.

All witnessed the terrible effects of the COVID-19 pandemic on the health and work lives of the population across the world. It is hard to diagnose all infected people in real time since the conventional medical diagnosis of COVID-19 patients takes a couple of days for accurate diagnosis results. In this paper, a novel learning framework is proposed for the early diagnosis of COVID-19 patients using hybrid deep fusion learning models. The proposed framework performs early classification of patients based on collected samples of chest X-ray images and Coswara cough (sound) samples of possibly infected people. The captured cough samples are pre-processed using speech signal processing techniques and Mel frequency cepstral coefficient features are extracted using deep convolutional neural networks. Finally, the proposed system fuses extracted features to provide 98.70% and 82.7% based on Chest-X ray images and cough (audio) samples for early diagnosis using the weighted sum-rule fusion method.

Negative capacitance field effect transistors (NCFETs) have attracted good attention for energy efficient circuit designs. However, there are no clear design insights with NCFET based circuit designs for energy efficient and hardware secure applications. However, the lack of clear design insights make energy efficient and hardware secure NCFET circuit design more challenging. This paper presents important design insights and scope of NCFETs for energy efficient and hardware secure logic design at scaled supply voltages. Initially, NCFET device characteristics have been analyzed by varying the ferroelectric layer thickness ( t fe ) to identify optimum device performance window. At 40 nm technology node, NCFET device demonstrates enhanced characteristics for logic design with t fe in the range of 3 nm–5 nm due to steep subthreshold swing characteristics. NCFET with t fe of 5 nm exhibits 1.22 × higher ON current, 66 × lower leakage current and a SS of 50mV/dec compared to baseline MOSFET ( t fe  = 0 nm). Further, NCFET based static complementary inverter design exhibits better performance and higher energy efficiency compared to baseline MOSFET. NCFET inverter with t fe of 3 nm achieves optimum performance in terms of voltage transfer characteristics, differential gain, and noise margins. In addition, NCFET with t fe of 3 nm shows minimum energy consumption with the different supply voltages in the range of 0.6–0.8 V. Moreover, NCFET based buffer, logic gates and half-adder designs with t fe of 3 nm achieve approximately 3 × lower energy consumption compared to baseline designs. Apart from this, the NCFET designs exhibit 2 × higher ON current variations, 12 × higher inverter delay variations, and 3.1 × higher ring oscillator frequency variations compared to baseline designs against 5% process parameter variations at a supply voltage of 0.5 V. With the higher variations resulted from ferroelectric layer, NCFET demonstrate the potential and suitability towards the design of hardware security primitives like physically unclonable function (PUF) and true random number generator (TRNG).

Perpendicular Magnetic Anisotropy-based Magnetic Tunnel Junction (PMA-MTJ) and Spin Transfer Torque Magnetic Random-Access Memory (STT-MRAM) have attracted wide attention among the next-generation Non-Volatile Memory (NVM) technologies due to low leakage and high-density characteristics for embedded memory architectures. However, STT-MRAM-based memory cells are not energy efficient with CMOS scaling at scaled supply voltages. This paper presents a novel energy-efficient Hybrid TFET (1 T: Hetero-junction TFET, 1 T: Homo-junction TFET)/STT-MRAM cell that explores p-i-n forward current of Tunnel FET. The proposed hybrid memory cell demonstrates ~27.3% energy efficiency over equivalent 1 T FinFET/STT-MRAM cell, 16.75% energy efficiency over equivalent 1 T Homo-junction TFET/STT-MRAM cell and 24.3% energy efficiency over equivalent 1 T Hetero-junction TFET/STT-MRAM cell at V = 0.5 V.

Conventional complementary metal oxide semiconductor (CMOS)-based dedicated true random number generator (TRNG) and physically unclonable function (PUF) designs have exhibited higher energy consumption and large area overhead with technology scaling. In contrast, this paper for the first time presents emerging tunnel field-effect transistor (TFET)-based ultra-lightweight reconfigurable TRNG and PUF design. A unique methodology is proposed that considers p-i-n forward current characteristics to generate random keys for PUF and TRNG designs. Leveraging the p-i-n forward current of TFET, a ring oscillator (RO) is designed that exhibits variation in the operating frequency and acts as the main source of entropy for both PUF and TRNG. The TRNG in the proposed design is robust and passed all the National Institute of Standards and Technology (NIST) tests. Considering the variation in p-i-n forward current, the uniqueness of PUF is calculated as 47.5% and 46% at a supply voltage of 0.5 and 0.45 V, respectively. Moreover, PUF achieves high reliability of 82% and 88.7% with supply voltage and temperature variations, respectively. The proposed design is proved to be compact with relatively lower gate count and shows low energy consumption of 4.8 pJ/bit at 0.5-V supply voltage. With these performance metrics, the proposed design is highly suitable for resource-constrained internet of things (IoT).

Emerging nanoelectronic semiconductor devices have been quite promising in enhancing hardware-oriented security and trust. However, implementing hardware security primitives and methodologies requires large area overhead and power consumption. Furthermore, emerging new attack models and vulnerabilities are regularly evolving and cannot be adequately addressed by current CMOS technology. This paper for the first time presents a comprehensive review of numerous post-CMOS technologies based hardware security primitives and methodologies, particularly true random number generators, physically unclonable functions, sidechannel analysis countermeasures, and hardware obfuscation techniques. Various beyond-CMOS device technologies including tunneling FET (TFET), hybrid phase transition FET (HyperFET), carbon nanotube FET (CNTFET), silicon nanowire FET (SiNWFET), symmetrical tunneling FET (SymFET), phase-change memory (PCM), spin-transfer torque magnetic tunnel junction (STT-MTJ), resistive random access memory (RRAM) have been considered in this study. First, the basic principle of operation and unusual characteristics of nanoelectronic devices used for hardware security applications have been extensively discussed. Later, CMOS technology challenges and benefits of emerging nanotechnologies for the design of hardware security primitives and methodologies have been reported. Finally, different analyses have been presented to demonstrate the promising performance of post-CMOS devices over the current CMOS technology in different countermeasures. Additionally, challenges, future directions, and plans have been presented to achieve more research outcomes in this field.

Accelerator is a hardware that runs along with the processor and executes the key functions much faster than the processor. The Main purpose of the Accelerator is to increase speed. Deep Neural Networks has achieved wide results in the various Machine Learning Applications Such as image, video, text classification and language translation. The purpose of DNN Accelerators is to speed up the most complex Computation i.e., matrix multiplication. Systolic array Based Accelerator seems like multiply Accumulate unit with Systolic Array based multiplication followed by Adder and accumulator. Multiply Accumulate Unit comprises multiplier, adder and Accumulator. Multiplier is designed used systolic array and that output is given as one of the inputs to the adder followed by Accumulator. In this paper general Matrix based Multiply Accumulate Unit is compared with systolic array based Multiply Accumulate Unit using Xilinx ISE 14.5, various parameters like area, delay and speed are compared. Systolic Array based Multiply Accumulate Unit consumes less area of 49%, less delay of 35% and in turn provides high speed when compared with general matrix multiplier-based multiplier Accumulate unit.

Analog-to-Digital Converter (ADC) design plays an important role for accurate and efficient interfacing of real-world signals for IoT platforms embedded with multiple sensors. In this paper, a Flash or direct conversion 4-bit and 5-bit ADCs are designed and implemented in 90nm CMOS. The performance of the flash ADC is evaluated against important performance metrices. The proposed 4-bit ADC achieve a power consumption of 1.41mW, SNR of 26.184dB, 3.71 ENOB and 16.19 pJ/step of FoM and 5-bit ADC achieve a power consumption of 2.921mW, SNR of 31.149dB, 4.51 ENOB and 19.12 pJ/step of FoM.

Negative capacitance field effect transistor (NCFET) is a promising technology which exhibits lower subthreshold swing (SS) and high ON current beyond the limit of conventional CMOS. However, the lack of design insights and rules make NCFET circuit design challenging. To address this, proposed work discusses several design insights and advantages of NCFET based logic for energy efficient electronics. NCFET device demonstrates enhanced characteristics for logic design with ferroelectric layer thickness (t_{fe}) in the range of 3nm to 5nm. At 45nm technology node, NCFET with tfe of 5nm exhibits 1.22\times higher ON current, 66\times lower leakage current and a lower SS (50mV/dec) compared to baseline MOSFET. In addition, NCFET based static complementary inverter exhibited optimum performance with tfe of 3nm. At a supply voltage of 0.5V, NCFET inverter demonstrates 3.3\times lower energy consumption compared to baseline inverter design. Furthermore, NCFET based logic gates (AND, OR, XOR) show at least 3\times lower energy consumption compared to baseline designs at 0.5V.

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Differential power analysis (DPA) has become an efficient side channel attack that obtains a secret key from the extracted power traces. Several traditional CMOS-based DPA countermeasures resulted in high area overhead and performance degradation. This study presents low area overhead DPA countermeasure exploring tunnel field effect transistors (TFET) based random number generator (RNG). TFET exhibits significant p-i-n forward current with an increase in negative drain-to-source voltage bias. It is demonstrated that TFET transmission gate exhibits unconventional behaviour due to p-i-n forward current of the device. Leveraging this behaviour TFET RNG is designed that extracts random bits from delay variations of the TFET ring oscillator. The proposed TFET RNG achieves low area overhead when compared with the baseline CMOS designs. The proposed DPA countermeasure is demonstrated by integrating the original TFET substitution box (S-box) and TFET RNG. The proposed architecture is found to be resilient to DPA attack and the area overhead of single S-box and Advanced Encryption Standard AES is as low as 12 and 5%, respectively. Apart from low area overhead, the TFET designs with inherent device characteristics show high robustness against reverse engineering attacks which provide a higher level of security to TFET-based circuits and systems.

Tunnel field-effect transistor (TFET) exhibits significant p-i-n forward leakage with the increase in drain-to-source voltage bias, and this adversely impacts the power consumption and reliability of TFET digital circuits. This work presents low-power circuit techniques that result in novel compact gates and recommends tristate gates to mitigate the leakage effects. The proposed novel compact gates and tristate gates demonstrate two and six times lower power consumption compared with conventional TFET transmission gates with enhanced reliability. Further, this work introduces a new design methodology that leverages TFET p-i-n forward leakage for hardware obfuscation applications. Utilizing the proposed design methodology, the optimization of 40% and 80% in area and power consumption of hardware security primitives like true random number generators is also accomplished.